Technical Field
This disclosure relates generally to clocking circuitry and more particularly to clock gating for dual-edge triggered circuits.
Description of the Related Art
Dual-edge triggered (DET) circuits are configured to perform activities on both rising and falling edges of a clock signal. For example, a DET flip-flop may be configured to accept and store an input value both when the clock rises and when it falls. DET circuitry may achieve a given performance threshold with half the clock frequency.
Clock gater circuits are configured to block clock signals to other circuitry (e.g., to reduce power consumption when other circuitry is not being used). Clock gaters are typically distributed throughout the clock tree of an integrated circuit in order to allow gating of the clock at different granularities to portions of the circuit. For DET circuitry, clock gaters may need to be able to begin gating the clock signal on either the rising or the falling edge, depending on when a gating signal is asserted. Therefore, a DET clock gater may operate in one of two states of modes, 1) where the output of the gater is inverted with respect to the input and 2) wherein the output of the gater is not inverted with respect to the input. Low power consumption is typically a desirable feature of clock gating circuitry. Further, DET clock gaters may have different delay in different operational modes, which may result in unbalanced clock signals to different circuit portions.